The field of the invention generally relates to test equipment pin drivers that produce driver pulses to test a device under test, and more particularly relates to an offset compensation circuit that limits output offset voltages in such pin drivers.
As is well known, the role of a pin driver in typical automatic test equipment (ATE) system is to send driver pulses having the correct voltages and timing to a device under test (DUT). One of the important parameters of such driver pulses is the offset voltage which is here defined as the difference between a high or low pulse voltage level VOH or VOL and the corresponding programmed or intended voltage level. In particular, the lower level VOL offset is the difference between the actual pulse voltage VOL in the lower or baseline level and the programmed lower voltage VL which is the intended magnitude origin line. Similarly, the upper level VOH offset is the difference between the actual pulse voltage VOH in the upper level and the programmed upper voltage VH. Offset voltages define driver pulse DC level errors and result in the pin of the device under test being either under or over driven. In most ATE systems, offset voltages higher than 30 millivolts requires automatic calibration which takes up valuable test time. Therefore, it is an important objective in ATE design to have extremely small offset voltages that are well within acceptable tolerances. That is, it is important to have accurate correspondence between the high and low voltage levels of the driver pulses and their corresponding programmed voltage levels VH and VL.
A prototype pin driver was built to include a pulse forming section, a buffer, and an amplifier connected in series. The pulse forming section received a data input and, in response thereto, provided output pulses timed in accordance with the data input. That is, the delay, width, and period of the output pulses were determined by the timing or transitions of the data input. The amplifier stage of the pin driver required a significant amount of input bias current. Therefore, in order to keep the amplifier output driver pulse parameters independent of the load, a buffer was connected between the pulse forming section and the amplifier. Without the buffer, the slew rate of the pulse forming section pulses would have been undesirably dependent upon the loading on the output of the amplifier. The slew rate is here defined as 60%(VOH-VOL)/T.sub.R where T.sub.R is the rise time between 20% and 80% values of (VOH-VOL).
In the above described prototype pin driver, clamp diodes were connected to a node at the input of the buffer to set the high and low voltage levels of the pulses in that stage. In particular, each diode was connected through an emitter to base junction of a respective emitter follower transistor to respective programmed high and low reference voltages VH and VL. The polarities of the clamping diodes were arranged with the intent that one would be forward biased and thereby clamp when the node rose to VH, and the other would be forward biased and thereby clamp when the node dropped to VL. The voltage drops across the respective clamping diodes were to be compensated by the voltage drops across the emitter to base junctions of the respective transistors. The above described prototype was tested, and it was determined that improvement in offset voltage was desirable.